Download PDF by Taoufik Bourdi: CMOS Single Chip Fast Frequency Hopping Synthesizers for

By Taoufik Bourdi

ISBN-10: 1402059272

ISBN-13: 9781402059278

During this booklet, the authors define specified layout method for quick frequency hopping synthesizers for RF and instant communications purposes. there's nice emphasis on fractional-N delta-sigma established part locked loops from necessities, procedure research and structure making plans to circuit layout and silicon implementation. The built innovations within the booklet may help in designing very low noise, excessive pace fractional-N frequency synthesizers.

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Read or Download CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation PDF

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Extra info for CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation

Example text

The PFD integrates frequency error to generate a duty cycle that in turn drives the CP model. The PFD model gives a duty cycle output that can take values in the range of −1 to +1. When the duty cycle is negative there is discharge to the loop filter and when the duty cycle is positive there is a charge to the loop filter. 48 Chapter 4 Figure 4-3. PFD/CP Characteristics Showing the Dead-Zone Region System Simulation of ∆−Σ -Based Fractional-N Synthesizers 49 The PFD/CP linearity curve, whether taking into account the deadzone or not, is provided by a lookup table immediately after the PFD.

Description of the charge pump mechanism in a PLL. -G. Goldberg. Digital Techniques in Frequency Synthesis, MacGrawHill, New Jersey, 1996. -G. Goldberg, “Analog and Digital Fractional-n PLL Frequency Synthesis: A Survey and Update,” Applied microwave and wireless, June 1999. Tutorial presenting fractional-N frequency synthesis. V. Brennan, Phase-Locked Loops, Principles and Practice, McGrawHill, New Jersey, 1996. [14] D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proceedings of the IEEE, MI, 54 (2), pp.

It can be seen from Figure 3-6 that the gain drops to 1 (0 dB) at the specified LBW frequency (100 kHz) and the phase is at its peak of −124o which corresponds to a phase margin of 56o (180o–124o). The loop filter transfer function Z(s) is also plotted in Figure 3-8. The gain of Z(s) shows the change in the 20 dB/decade slope for fp /10 (10 kHz) and 10fp (1 MHz). 10 Figure 3-6. 10 Figure 3-7. 10 Figure 3-8. 10 26 Chapter 3 The time-domain function for the closed-loop transfer function can be obtained by performing an inverse Laplace transform.

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CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation by Taoufik Bourdi


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