Download e-book for kindle: CMOS Multichannel Single-Chip Receivers for Multi-Gigabit by Paul Muller, Yusuf Leblebici

By Paul Muller, Yusuf Leblebici

ISBN-10: 1402059116

ISBN-13: 9781402059117

ISBN-10: 1402059124

ISBN-13: 9781402059124

On the planet of optical info communications this e-book could be an absolute must-read. It makes a speciality of optical communications for brief and intensely brief distance purposes and discusses the monolithic integration of optical receivers with processing components in usual CMOS applied sciences. What’s extra, it offers the reader with the required history wisdom to completely comprehend the trade-offs in short-distance conversation receiver layout and offers the main concerns to be addressed within the improvement of such receivers in CMOS applied sciences. in addition, novel layout techniques are provided.

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Additional info for CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing)

Example text

G. drain junction capacitance Cd) which do not shrink as much as the gate from one technology node to the next, it represents an optimistic estimate of technology performance in RF and wireline applications. 2). This parameter takes into account the parasitic drain capacitance that scales less efficiently than the gate dimensions. However, it is rarely published by the foundries, reducing its usage in a priori comparison of technology performance. 2 for a comparison of supply voltages between CMOS and bipolar processes).

G. drain junction capacitance Cd) which do not shrink as much as the gate from one technology node to the next, it represents an optimistic estimate of technology performance in RF and wireline applications. 2). This parameter takes into account the parasitic drain capacitance that scales less efficiently than the gate dimensions. However, it is rarely published by the foundries, reducing its usage in a priori comparison of technology performance. 2 for a comparison of supply voltages between CMOS and bipolar processes).

Several phase detector circuit topologies 18 Basic Concepts for phase-locked loops (PLL) operating on random data streams have been developed. These structures, performing implicit edge detection at the input of the PLL, are discussed in more detail in [19]. 8. Explicit edge detection of NRZ data It is important for the reader to understand that the sampling instant determined by the rising clock edge (respectively the falling clock edge in some designs) is considered as the reference point in time for measurement of jitter and bit error ratio.

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CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing) by Paul Muller, Yusuf Leblebici


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