Download e-book for iPad: Analog Circuit Design - High-Speed Clock And Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

ISBN-10: 1402089430

ISBN-13: 9781402089435

Analog Circuit layout includes the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and necessary layout rules within the region of analog circuit layout. each one half is gifted via six specialists in that box and state-of-the-art details is shared and overviewed. This booklet is quantity 17 during this winning sequence of Analog Circuit layout.

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Additional info for Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management

Example text

With the above mentioned techniques, the jitter tolerance has been optimized in presence of a slope in the frequency drift, as in case of SSC. On the other hand, Cyclic Accum. CA Demuxed C Ndmx Z Kp Coder -1 FF FF Early-Late Count FF Demuxed E Ndmx X2 X1 X05 NPH phases FF Transition Count Ki Z -1 1/Ks Ival FF 1 Fig. 21 CDR jitter optimization 2 3 FF C E A 30 M. Pozzoni et al. Cyclic Accum. CA Demuxed C Ndmx Z Kp Early-Late Count Demuxed E Ndmx Coder -1 FF FF Ni FF FF Fast Lock X2 X1 X05 0 Ni FF Transition Count FF Double Step Decimator Ki Z -1 1/Ks Ival NPH phases Fast Lock Fig.

24 M. Pozzoni et al. Equalization partitioning takes into account ISI, crosstalk and reflections by means of S-parameters analysis. A random received eye is computed for different configurations of transmission channels and interference to assure a target bit error rate lower than 1e-12. The best partition between the analog block and DFE follows. Verification of system performances, including both equalization and clock recovery, leads to the second step, consisting in VHDL modeling and simulation of the whole system.

The clock and data recovery in the RX uses a phase interpolator and digital loop filter to lock to the incoming data stream [6, 7]. In a bang-bang phase detector the data and data edge are sampled from a phase interpolators clock signal that can be varied in 32 phase steps. The Fast and Reliable Serdes Developments in nm Technologies 45 data clock LR PD deserializer 8 early late digital loop filter 32 phase interpolator quadrature full rate clock Fig. 8 PCI-Express RX architecture using a digital loop filter and phase interpolator for CDR obtained early-late signals are downsampled with a factor 8 and then accumulated in a digital loop filter.

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Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier


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